1. Technical Field
The field of the invention is that of fabricating integrated circuits, in particular forming the interconnect structures in the back end of the line (BEOL).
2. Background of the Invention
In the course of developing copper interconnects for use in the back end of silicon, integrated circuits, it became necessary to encapsulate the copper interconnect material with a diffusion barrier in order to prevent the copper from escaping from the damascene channel. Because of the significant diffusion mobility of Cu atoms in most insulators, a small amount of Cu can cause serious short circuit problems in an integrated circuit. A small amount of Cu can further damage the function of devices completely when it diffuses into the well-defined implanted device areas.
Extensive work was done that resulted in a compatible system in which the copper was encased with a liner formed of a material having good diffusion blocking properties, such as one of the refractory metals, e.g. Ti, Ta or nitrides of those and similar metals.
However, these compounds have a high resistivity compared with copper and also have presented an electrical problem at the interface between adjacent back end layers.
A recurring problem with these interfaces is electromigration, in which atoms move under the influence of the electric field applied to the material. This material transport causes a significant number of circuit failures. The back end structures are built to carry electrical signals, of course, so that the existence and magnitude of the applied fields cannot be changed.
FIG. 1A illustrates a dual damascene structure in the prior art, in which a lower level 100, containing a copper interconnect 110 extending perpendicular to the plane of the paper has a cap layer 120. In the next layer above, interlevel dielectric (ILD) 130 has had a dual damascene aperture formed in it with a lower part 148 and a broader upper part 150. Illustratively, the ILD is silicon oxide or a low k dielectric such as SiLK, SiCOH, or any other kind of hybrid related materials. Aperture 148 is illustratively a via making contact with the lower structure and will be located at only a few locations. Upper portion 150 will extend over a significant distance to make contact with other elements of the circuit as required by the layout. In this figure, the portion of the cap layer 120 at the bottom of aperture 148 has been removed, usually by a different etching chemistry from that used to etch through the ILD.
Since the open surface of the metal underneath aperture 148 is a potential weak point, it is conventional to deposit a liner 160, shown in FIG. 1B, over the entire interior of the upper structure. Liner 160 may be TiN or a similar diffusion barrier, optionally including an adhesion layer that bonds well to the ILD. The liner is needed to confine the copper in the patterned ILD, i.e. both 150 and 148.
FIGS. 2A and 2B show similar figures for the case of a single damascene interconnect structure.
Problems with this prior art approach have been failure to make a good mechanical contact (leading to an open circuit or to a high resistance joint) at a chip operating temperature. Failures also include a poor electromigration resistance at the joint because of high resistivity that slows down the rise time of a signal or otherwise interferes with the electrical properties of the circuit.